The present invention relates to a system for testing a data-processing unit which is able to be connected to at least one other data-processing unit and to certain optional members.
The present application is a continuation of the parent U.S. application Ser. No. 450,936, filed Mar. 13, 1974, and further, claims priority under 35 USC 119 to the filing date of the corresponding French patent application.
Data-processing units generally incorporate an erasable store and a permanent store which may contain microprogrammes and testing the units calls for a very large number of operations. These operations generally consist of loading a test programme into the erasable store of the data-processing unit to be tested from a peripheral device, this being done either when the unit has been set to some initial state or in the course of processing when a functional error detector detect an error and the error automatically stops the clock circuits of the unit in question. Data is transmitted to the various elements of the unit to be tested, possibly by means of test microinstructions contained in the permanent store, in order to produce signals representative of the state of these elements. These signals, which may come from functional error detectors, are then compared with reference signals which represent the correct functioning of the elements being tested. Testing each element thus results in a switching signal which either causes the next test operation to be selected if the element which has just been tested is operating correctly, or causes the tests to be suspended or the unit in question to cease processing entirely when an error is detected. When an error is detected the diagnosis to locate the fault is thus based on the elements already tested.
Test systems of this type have a number of drawbacks. Firstly, the fact of having to load a test programme into the erasable store associated with the unit to be tested from a peripheral device necessitates a relatively lengthy operation and makes it especially difficult to trace intermittent faults. Secondly, the loading of the programme may be carried out incorrectly and this may result in omission in the writing of the programme or in erroneous data being written. In this way the testing of the unit may be falsified, as may also be the results obtained. The absence of any means of checking the progress of the tests may also be a source of error which known test systems are incapable of detecting. Nor do such systems contain any means which allow a data-processing unit to be tested from an initial reference state taken of by its storage elements. Thus, the actual initial state of the unit in question may be different from the initial state on the basis of which the reference data in the test programme was calculated, thus falsifying the results of the comparisons by means of which a fault is located. Stopping the clock circuits of the unit in question when an error is detected is also a major inconvenience since any diagnosis process to locate a defective component can only be based on part already tested. The same component may in fact participate in the operation of a number of elements to be tested and the testing of one element may call into play a number of components. If one of these components is defective, the diagnostic process to locate a fault must be performed by a long and painstaking process of dichotomy.
To overcome these drawbacks, one of the objects of the present invention is to make it possible for tests carried out automatically and at high speed on a unit, in the event of an error being detected during processing.
A further object of the invention is to enable all the symptoms required for the immediate location of a fault in a data-processing unit to be collected together.
Another and essential object of the invention is to produce a reliable test system in which all the storage elements of the data-processing unit to be tested are automatically set into a predetermined initial state before the beginning of the testing procedure per se.